1. Field of the Invention
The present invention relates generally to semiconductor devices including an insulated gate field effect transistor (hereinafter referred to as an MIS transistor) and particularly to configurations for reducing power consumption in semiconductor devices having microfabricated CMOS transistors (p and n channel MIS transistors). More specifically, the present invention relates to configurations for reducing gate tunneling current of microfabricated MIS transistors.
2. Description of the Background Art
In CMOS semiconductor devices including CMOS transistors as a component, if an MIS transistor is significantly scaled down in size, an operating power supply voltage is reduced in order to ensure the reliability of the transistors and to achieve reduced power consumption. When the size of MIS transistor is reduced in accordance with the reduction of the operating power supply voltage, each parameter value of the transistors is reduced in accordance with a predetermined scaling rule.
According to such scaling rule, the MIS transistor is required to have a gate insulation film reduced in thickness, Tox, and a threshold voltage, Vth, reduced in absolute value. However, a threshold voltage cannot be reduced in absolute value in accordance with the scaling rule. The threshold voltage is defined as a gate to source voltage causing a prescribed drain current under application of a predetermined drain voltage.
When the threshold voltage Vth is reduced in absolute value and if a gate to source voltage Vgs attains 0V, a weak inversion layer is formed in a channel region and through this inversion layer a subthreshold current (hereinafter referred to as an “off-leak current”) flows. The off-leak current increases as the threshold voltage decreases in absolute value. Accordingly, in a standby cycle in which MIS transistor is kept off, the off-leak current increases and a standby current increases disadvantageously. In particular, for portable equipment or other battery-driven equipment employing such a semiconductor device, reducing the off-leak current is a significant issue to increase the lifetime of a battery.
When the off-leak current is reduced by increasing the threshold voltage Vth in absolute value, an advantage achieved by reduced operating power supply voltage cannot be insured, and high speed operation cannot be ensured. A multi-threshold CMOS (MT-CMOS) configuration has been proposed, for example in Japanese Patent Laying-Open No. 6-29834, to reduce an off-leak current in the standby cycle and also ensure high speed operation.
In the MT-CMOS configuration proposed in the prior art document, a transistor having a threshold voltage M-Vth with a relatively large (intermediate) absolute value is connected between a main power supply line and a sub power supply line as a power supply switching transistor. A logic circuit is constructed of L-Vth transistors each having a threshold voltage with a small absolute value. In such logic circuit, a transistor kept off in the standby cycle is connected to the sub power supply line and a transistor kept conductive in the standby state is connected to the main power supply line.
In the standby cycle, the power supply switching transistor is kept in the off state. In the standby cycle, the voltage level of the sub power supply line is set to be a voltage level making the off-leak current of the power supply switching transistor balancing that of the transistors of the logic circuit. Therefore, due to the voltage drop at the power supply switching transistor, the transistor connected to the sub power supply line of the logic circuit has a gate to source voltage reversely biased to enter a more stronger off state. Thus, the off-leak current is further reduced, in conjunction with the small off-leak current of the power supply switch transistor.
In an active cycle, in which an operation is actually performed, the power supply switching transistors is set to the on state, the sub power supply line is connected to the main power supply line. Thus, the logic circuit, constructed of transistors having a threshold voltage with a small absolute value, operates at high speed.
Japanese Patent Laying-Open No. 9-116417 discloses that in order to set the power switching transistors to a stronger off state in the MT-CMOS configuration, a high voltage VPP higher than an H level power source voltage VDD is applied to a power switching transistor provided to the power supply voltage VDD, and a negative voltage VBB is applied to a power switching transistor provided for an L level power source voltage VSS.
Various parameters of an MIS transistor, such as feature size, are scaled down in accordance with a scaling rule. Such scaling rule stands on the premise that the gate length and the thickness of the gate insulation film of the MIS transistor are scaled down in accordance with a common shrinking rate. For example, an MIS transistor having a gate length of 0.25 μm has a gate insulation film generally having a thickness of 5 nm. Accordingly, an MIS transistor having a gate length of the order of 0.1 μm has a gate insulation film having a thickness of the range of 2.0 to 2.5 nm.
If a gate insulation film is reduced in thickness as an operating power supply voltage is reduced, e.g., the gate insulation film is reduced to substantially 3 nm under the condition of a power supply voltage of no more than 1.5V, a tunneling current flows through the gate insulation film of the MIS transistor in the on state (conductive state) and a power source current through the transistor in the on state increases disadvantageously.
Japanese Patent Laying-Open No. 11-150193 discloses that such a gate tunneling leak current might be reduced by a control circuit constructed of an MIS transistor of a thick gate insulation film and controlling turning on/off of the power switching transistor.
FIGS. 30A to 30C schematically show an energy band of an MIS structure. FIGS. 30A to 30C show, as an exemplary energy band, a band for a structure with a gate formed of a metal. Typically, in an MIS structure, a gate is formed of polysilicon doped with an impurity and has a property of semiconductor. However, to simplify the description, the gate is assumed to be formed of metal. In addition, the semiconductor substrate region is a p type substrate.
As shown in FIG. 30A, if the gate receives a negative voltage V, holes present in the p type substrate are attracted to an interface with the insulation film and the energy band of the p type substrate bends, at the interface between the insulation film and the p substrate, upward and a valence band Ev approaches a Fermi level EF. Furthermore, a conduction band Ec also bends upward in a vicinity of this interface.
When the negative voltage is applied, the Fermi level EF of the gate (corresponding to conduction band Ec for a polysilicon gate) also increases. In this condition, in the p type substrate, the density of majority carriers (holes) is increased at the interface, as compared with an inside thereof, and such state is referred to as an accumulated state. In this state, the conduction band Ec bends upward and a barrier against electrons is increased in height, and no current tunnels through the gate insulation film.
As shown in FIG. 30B, when the gate receives a low positive voltage V, the Fermi level EF (valence band Ec) of the gate decreases and responsively the p type substrate region also has the conduction band Ec and the valence band Ev banding downward at its interface with the insulation film. Holes are moved away from the interface with the insulation film, to cause the poor state of majority carriers (holes). Fermi level EF at the interface is positioned substantially at the center of a forbidden band and no majority carrier is present, and such a state is referred to as a “depletion state.” In the depletion state, no carrier is present at an interface and, similarly, a tunneling current is not generated.
As shown in FIG. 30C, when the gate receives a larger positive voltage V, the Fermi level EF at the gate is further reduced and in the p type substrate, the band bending further increased in a vicinity of the interface. Consequently, in the vicinity of the interface of the p type substrate, Fermi level EF is increased to be higher than an intermediate value Eg/2 of an energy gap Eg and minority carriers, or electrons, are stored. Since the interface is opposite in conductivity to an inside, this state is referred to as an “inverted state.”
This inverted state corresponds to a state of a channel being formed in an MIS transistor, and if the gate insulation film has a thickness 6, for example, of 3 nm, the minority carriers, or electrons, cause the tunneling phenomenon and flows to the gate. In other words, in an MIS transistor with a channel being formed, i.e., an MIS transistor in the on state, a tunneling current flows from a channel region to the gate directly. This tunneling current is referred to as a (direct) gate tunnel current.
This issue of disadvantageous gate tunnel current similarly applied to an n type substrate region, with the modification that the gate receives a voltage opposite in polarity and the energy band bends in the opposite directions.
As described above, if an MIS transistor has a gate insulation film reduced in thickness to 3 nm, for example, a gate tunnel current directly flows from the channel region to the gate. This gate tunnel current becomes the same in magnitude as an off-leak current when the gate insulation film has a thickness of the order of 3 nm. When the gate insulation film is reduced in thickness below 3 nm, the gate tunnel current increases to be greater in magnitude than the off-leak current. Thus, if an operating power supply voltage is decreased and a gate insulation film is reduced in thickness in accordance with a scaling rule, this gate tunnel current attains an insignificant value and accordingly, a current consumed in the standby cycle increases.
A gate tunnel current J satisfies a relationship approximately represented by the following expression:J˜E·exp[−Tox·A·√{square root over (φ)}],where φ represents a height of a barrier of an interface of the gate insulation film and approximately represented by a difference between a surface potential φs of the interface and Fermi level, A represents a constant determined by a concentration of an impurity (an effective mass of an electron) of a semiconductor substrate of a channel region, and E represents an electric field applied across the gate insulation film.
The barrier height φ is a function of a dielectric constant ε of the gate insulation film and thickness Tox of the gate insulation film. For example, if silicon oxide film is used to form the gate insulation film and the tunnel current flows at the thickness of 3 nm, such a gate tunnel current is also caused to flow in a gate insulation film providing the same barrier height as the silicon oxide film of 3 nm thickness. The gate insulation film can be formed of silicon oxinitride film, other than silicon oxide film.
If such a microfabricated MIS transistor is included as a component, the gate tunnel current of MIS transistor attains to be same as or greater in amount than an off-leak current in the standby state and a current consumed in the standby cycle cannot be reduced.
FIG. 31 shows a configuration of the MT-CMOS circuit disclosed in Japanese Patent Laying-Open No. 11-150193. In FIG. 31, a logic circuit is constructed of CMOS inverters IVa and IVb cascaded in two stages, by way of example. CMOS inverters IVa and IVb each include a p channel MIS transistor QPT having a source connected to a sub power supply line SPL and an n channel MIS transistor QNT having a source connected commonly to a sub ground line SGL. MIS transistors QPT and QNT in inverters IVa and IVb are each made to have a gate insulation film less than 2.5 nm in thickness.
Sub power supply line SPL is connected to a main power supply line MPL via a power supply switching transistor PS, and sub ground line SGL is connected to a main ground line MGL via a power supply switching transistor NS. Power supply switching transistor NS has its gate receiving a switch control signal SWCT, and power supply switching transistor PS has its gate receiving switch control signal SWCT via a CMOS inverter CIV. CMOS inverter CIV includes p and n channel MIS transistors each having a gate insulation film set to be not smaller than 4 nm in thickness. CMOS inverter CIV receives a power supply voltage VCC on main power supply line MPL and a ground voltage on main ground line MGL as operating power supply voltages. In other words, in CMOS inverter CIV, the p channel MIS transistor has its source connected to main power supply line MPL, and the channel MIS transistor has its source connected to main ground line MGL.
Power supply switching transistors PS and NS have their gate insulation films set to be not smaller than 2.5 nm in thickness.
In the configuration of FIG. 31, in a standby state, switch control signal SW attains an L level (logical low level), and CMOS inverter CIV outputs a signal of an H level (logical high level). Responsively, power supply switching transistors NS and PS both turn off. Sub power supply line FPL and sub ground line SCL are each set to a floating state, and the output states of inverters IVa and IVb become unstable.
The voltage levels of sub power supply line SPL and sub ground line SGL in the standby state are determined by a leak current of the logic circuit. Transistor parameters vary within a permissible range for each chip, the voltage levels of the sub power supply and ground lines cannot be maintained at predetermined voltage levels. Accordingly, the sub ground and power supply lines are different in voltage for different chips, and inverters IVa and IVb, when transitioning to an active cycle, are different in output voltage level. Thus, it is necessary to determine a circuit operation timing with a worst case considered, and high speed and stable operation cannot be achieved.
Furthermore, in Japanese Patent Laying-Open No. 11-150193, in order to reduce the gate leak current in inverters IVa and IVb, well regions of MIS transistors QPT and QNT are isolated from each other. This results in a disadvantageously increased layout area in the case of an increased number of stages of inverters IVa and IVb.
Moreover, gate to source voltage Vgs of each of power supply switching transistors PS and NS in a conductive state is the power supply voltage VCC level. If power supply voltage VCC is set to an L level, power supply switching transistors PS and NS cannot enter a sufficiently deep on state and, in the active cycle, sub power supply and ground lines SPL and SGL cannot be held stably at prescribed power supply and ground voltage levels, respectively. In particular, if power supply noise is generated, the noise cannot be absorbed rapidly, a circuit cannot be operated stably, and the noise reduces a circuit operating margin.
Furthermore, if driving ability of the power supply switching transistor cannot be increased sufficiently, the sub power supply and ground lines cannot be driven rapidly to prescribed voltage levels in transition from the off state to an on state. Consequently, a certain period of time is required before an operation starts, which is an obstacle against high speed operation.